The present invention relates generally to a memory device using a single transistor and its fabrication method, in which the transistor comprises a source(S), a drain(D), and a ferroelectric gate(G) which are formed in a P type(or N type) well substrate for reading/writing data. The P type(or N type) well substrate is formed by diffusing doping sources. More particularly, the present invention relates to a non-volatile, non-destructive read-out memory device, which may read out a stored data without destroying the data, and its fabrication method.
The subject matter of the present application is disclosed in U.S. Pat. No. 5,559,733, filed Jun. 7, 1995 and U.S. Pat. No. 5,686,745, filed Jun. 19, 1995.
In general, a semiconductor memory is called a dynamic RAM(DRAM). The DRAM is a device capable of storing/choosing for reading the data by using a memory cell. Here, the memory cell comprises a transistor and a capacitor. Additionally, the DRAM performs a large capacity of memory function as integrating the memory cells. An integration rate of the memory cell now becomes higher and higher continuously according to technology of a very large scale integration(VLSI).
The DRAM always leads a most advanced microelectronic technology symbolized by device miniaturizing process, subminiature device and circuit design technology. The DRAM is a device of a mass product because a general manufacturing; process is stabilized and a circuit design is rarely changed. Advance of the device miniaturization shows an increment of the DRAM integration rate. Since 1 Kbyte DRAM showed in the 1970s, the capacity of the DRAM is increased almost 4 times of it at every 3 years and finally, the prototype of 1 Giga DRAM was realized in 1998. The high integration and large capacity of the DRAM are established by a bipolar transistor technology in the 1960s, in which the bipolar transistor may be operated with a high-speed even though it requires a large usage power. But an MOS technology is practically used because the manufacturing process is simple and requires low power dissipation since 1970s, and a CMOS technology having better low power dissipation, is now applied in the DRAM.
FIG. 1 is a circuitry diagram of a memory cell of a DRAM.
Referring to FIG. 1, the DRAM comprises a transistor as a switch, and a capacitor for storing data. A word line 1 is selected by an X-Address and a bit line 2 is selected by a Y-Address on a semiconductor memory which is fabricated by integrating the memory cells. Thereby, a cell data of the selected location is amplified and read externally. Binary xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d states, which are switched by applying a voltage pulse of sufficient magnitude. Here, binary information xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is corresponded to whether the capacitor of the memory cell has a charge or not, in other words, a terminal voltage of the cell capacitor is higher or lower than a predetermined value.
When the voltage in accordance with the binary information is applied to the memory cell, xe2x80x9cwritexe2x80x9d process is performed. And what the capacitor has the charge or not causes the voltage change to higher or lower, thereby xe2x80x9creadxe2x80x9d process is performed as a detecting it to an external memory cell. Data maintenance has ideally no power usage because the capacitor accumulates the charges.
But, there is a leak current in a PN junction of the MOS transistor, and the stored initial charge is therefore reduced. As a result, the data is lost. Accordingly, before losing the data, the capacitor should be recharged as much as the initial charge by matching the read information after reading the data of the memory cell. The memory maintains the data by which the above procedures should be repeated periodically. The recharging process is called refresh operation. The DRAM(Dynamic-RAM) is called because the data maintenance is dynamically accomplished through the repetition of the refresh operation.
In addition to the DRAM, there are a static RAM(SRAM), a ferroelectric RAM(FRAM), etc. The SRAM is used in a main memory of a supercomputer or a cache memory of a common calculator or a cache memory having a microprocessor, because of having durability of the information storage. And also it is commonly used for portable devices because the SRAM requires a low usage power for storing the data, even though there are disadvantages that manufacturing procedure is more complicated and it is more expensive than the DRAM to manufacture.
The FRAM is a new memory device which may successively store the data as using a memory cell, similar to DRAM, without supplying a power source. There are two kinds of FRAM; a destructive and a non-destructive type. The destructive FRAM comprises a transistor as a switch for reading/writing information and a capacitor of storing data. The destructive FRAM is similar to the DRAM except that the destructive FRAM uses a ferroelectric material as a capacitor. The ferroelectric material generates a spontaneous polarization without power source, it is therefore possible to have a continuous storage ability because of maintaining an electric characteristic successively. However, it should be required to reset that the information should be rewritten when the information stored in the capacitor is destroyed.
The non-destructive FRAM may perform a switching function with a single transistor as well as an information storage function, as an absolutely new memory device.
Accordingly, the non-destructive FRAM having a very simple structure, may improve an integration rate 10 times, comparing with the conventional DRAM or the destructive FRAM which have a single transistor and a single capacitor. The non-destructive FRAM including advantages of the DRAM and the destructive FRAM, may successively store information without power source, may use for a long time because of not requiring the reset function, and helps to establish a simple circuit.
However, it has not been invented the device structure, its fabrication method, and the subsidiary circuit of the non-destructive FRAM consisting of a single transistor for reading/writing information.
This invention is to resolve the problems described earlier and an object of the present invention is to provide the memory device structure, the fabrication method, and the subsidiary circuit of the non-destructive FRAM consisting of a single transistor for reading/writing information. The single transistor consists of a source, a drain, a ferroelectric gate, and a P type (or N type) well substrate. The ferroelectric gate and P type (or N type) well substrate are using for inputting(writing) information and a source and a drain are using for outputting(reading) information. Therefore, the memory, device has four terminals. In other words, the subsidiary circuit uses the four terminals for writing and reading information; two terminals (a gate and a substrate) for writing and two terminals (a source and a drain) for reading.